CY8C3866AXI-038 ic芯片解密

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　　Pin Descriptions
　　IDAC0, IDAC2. Low resistance output pin for high current DACs
　　(IDAC).
　　OpAmp0out, OpAmp2out. High current output of uncommitted
　　opamp[4].
　　Extref0, Extref1. External reference input to the analog system.
　　OpAmp0-, OpAmp2-. Inverting input to uncommitted opamp.
　　OpAmp0+, OpAmp2+. Noninverting input to uncommitted
　　opamp.
　　GPIO. General purpose I/O pin provides interfaces to the CPU,
　　digital peripherals, analog peripherals, interrupts, LCD segment
　　drive, and CapSense[4].
　　I2C0: SCL, I2C1: SCL. I2C SCL line providing wake from sleep
　　on an address match. Any I/O pin can be used for I2C SCL if
　　wake from sleep is not required.
　　I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleep
　　on an address match. Any I/O pin can be used for I2C SDA if
　　wake from sleep is not required.
　　Ind. Inductor connection to boost pump.
　　kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.
　　MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33 MHz crystal oscillator pin.
　　nTRST. Optional JTAG Test Reset programming and debug port
　　connection to reset the JTAG connection.
　　SIO. Special I/O provides interfaces to the CPU, digital peripherals
　　and interrupts with a programmable high threshold voltage,
　　analog comparator, high sink current, and high impedance state
　　when the device is unpowered.
　　SWDCK. Serial Wire Debug Clock programming and debug port
　　connection.
　　SWDIO. Serial Wire Debug Input and Output programming and
　　debug port connection.
　　SWV. Single Wire Viewer debug output.
　　TCK. JTAG Test Clock programming and debug port connection.
　　TDI. JTAG Test Data In programming and debug port
　　connection.
　　TDO. JTAG Test Data Out programming and debug port
　　connection.
　　TMS. JTAG Test Mode Select programming and debug port
　　connection.
　　USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
　　May be used as a digital I/O pin. Pins are No Connect (NC) on
　　devices without USB.[2]
　　USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
　　May be used as a digital I/O pin. Pins are No Connect (NC) on
　　devices without USB.[2]
　　Vboost. Power sense connection to boost pump.
　　Vbat. Battery supply to boost pump.
　　Vcca. Output of analog core regulator and input to analog core.
　　Requires a 1 雾 capacitor to Vssa. Regulator output not for
　　external use.
　　Vccd. Output of digital core regulator and input to digital core.
　　Requires a capacitor from each Vccd pin to Vssd; see Power
　　System on page 25. Regulator output not for external use.
　　Vdda. Supply for all analog peripherals and analog core
　　regulator. Vdda must be the highest voltage present on thedevice. All other supply pins must be less than or equal to
　　Vdda.
　　Vddd. Supply for all digital peripherals and digital core regulator.
　　Vddd must be less than or equal to Vdda.
　　Vssa. Ground for all analog peripherals.
　　Vssb. Ground connection for boost pump.
　　Vssd. Ground for all digital logic and I/O pins.
　　Vddio0, Vddio1, Vddio2, Vddio3. Supply for I/O pins. See
　　pinouts for specific I/O pin to Vddio mapping. Each Vddio must
　　be tied to a valid operating voltage (1.71V to 5.5V), and must be
　　less than or equal to Vdda. If the I/O pins associated with Vddio0,
　　Vddio2 or Vddio3 are not used then that Vddio should be tied to
　　ground (Vssd or Vssa).
　　XRES (and configurable XRES). External reset pin. Active low
　　with internal pullup. In 48-pin SSOP parts, P1[2] is configured as
　　XRES. In all other parts the pin is configured as a GPIO