AT89C51CC02芯片破解

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　　AT89C51CC02　描述：

　　Part of the CANaryTM family of 8-bit microcontrollers dedicated to CAN network applications,the T89C51CC02 is a low-pin count 8-bit Flash microcontroller.In X2 Mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.Besides the full CAN controller T89C51CC02 provides 16K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 512 Bytes RAM.Special attention is payed to the reduction of the electro-magnetic emission ofT89C51CC02.

　　AT89C51CC02　特征：

　　80C51 Core Architecture

　　256 Bytes of On-chip RAM

　　256 Bytes of On-chip XRAM

　　16K Bytes of On-chip Flash Memory

　　– Data Retention: 10 Years at 85°C

　　– Erase/Write Cycle: 100K

　　Boot Code Section with Independent Lock Bits

　　2K Bytes of On-chip Flash for Bootloader

　　In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability

　　2K Bytes of On-chip EEPROM

　　– Erase/Write Cycle: 100K

　　14-sources 4-level Interrupts

　　Three 16-bit Timers/Counters

　　Full Duplex UART Compatible 80C51

　　Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)

　　Three or Four Ports: 16 or 20 Digital I/O Lines

　　Two-channel 16-bit PCA

　　– PWM (8-bit)

　　– High-speed Output

　　– Timer and Edge Capture

　　Double Data Pointer

　　21-bit Watchdog Timer (7 Programmable bits)

　　A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs

　　Full CAN Controller

　　– Fully Compliant with CAN rev.# 2.0A and 2.0B

　　– Optimized Structure for Communication Management (Via SFR)

　　– 4 Independent Message Objects

　　-Each Message Object Programmable on Transmission or Reception

　　-Individual Tag and Mask Filters up to 29-bit Identifier/Channel

　　-8-byte Cyclic Data Register (FIFO)/Message Object

　　-16-bit Status and Control Register/Message Object

　　-16-bit Time-Stamping Register/Message Object

　　-CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object

　　-Access to Message Object Control and Data Registers Via SFR

　　-Programmable Reception Buffer Length up to 4 Message Objects

　　-Priority Management of Reception of Hits on Several Message Objects Simultaneously (Basic CAN Feature)

　　-Priority Management for Transmission

　　-Message Object Overrun Interrupt

　　– Supports

　　-Time Triggered Communication

　　-Autobaud and Listening Mode

　　-Programmable Automatic Reply Mode

　　1-Mbit/s Maximum Transfer Rate at 8 MHz(1) Crystal Frequency In X2 Mode

　　Readable Error Counters

　　Programmable Link to On-chip Timer for Time Stamping and Network Synchronization

　　Independent Baud Rate Prescaler

　　Data, Remote, Error and Overload Frame Handling

　　Power-saving Modes

　　– Idle Mode

　　– Power-down Mode

　　Power Supply: 3 Volts to 5.5 Volts

　　Temperature Range: Industrial (-40° to +85°C)

　　Packages: SOIC28, SOIC24, PLCC28, VQFP32